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eBook Details:
Full title: Fundamentals of Logic Design, Enhanced Edition, 7th Edition
Edition: 7th
Copyright year: 2021
Publisher: Cengage Learning
Author: Charles H. Roth, Jr.; Larry L Kinney; Eugene B. John
ISBN: 9780357381830, 9780357381830
Format: PDF
Description of Fundamentals of Logic Design, Enhanced Edition, 7th Edition:
Master the principles of logic design with the exceptional balance of theory and application found in Roth/Kinney/John’s FUNDAMENTALS OF LOGIC DESIGN, ENHANCED, 7th Edition. This edition introduces you to today’s latest advances. The authors have carefully developed a clear presentation that introduces the fundamental concepts of logic design without overwhelming you with the mathematics of switching theory. Twenty engaging, easy-to-follow study units present basic concepts, such as Boolean algebra, logic gate design, flip-flops and state machines. You learn to design counters, adders, sequence detectors and simple digital systems. After mastering the basics, you progress to modern design techniques using programmable logic devices as well as VHDL hardware description language.Important Notice: Media content referenced within the product description or the product text may not be available in the ebook version.
Table of Contents of Fundamentals of Logic Design, Enhanced Edition, 7th Edition PDF ebook:
DedicationContentsPrefaceHow to Use This Book for Self-StudyDigital ResourcesAbout the AuthorsUnit 1: Introduction Number Systems and ConversionObjectivesStudy Guide1.1 Digital Systems and Switching Circuits1.2 Number Systems and Conversion1.3 Binary Arithmetic1.4 Representation of Negative Numbers1.5 Binary CodesProblemsUnit 2: Boolean AlgebraObjectivesStudy Guide2.1 Introduction2.2 Basic Operations2.3 Boolean Expressions and Truth Tables2.4 Basic Theorems2.5 Commutative, Associative, Distributive, and DeMorgan’s Laws2.6 Simplification Theorems2.7 Multiplying Out and Factoring2.8 Complementing Boolean ExpressionsProblemsUnit 3: Boolean Algebra (Continued)ObjectivesStudy Guide3.1 Multiplying Out and Factoring Expressions3.2 Exclusive-OR and Equivalence Operations3.3 The Consensus Theorem3.4 Algebraic Simplification of Switching Expressions3.5 Proving Validity of an EquationProgrammed Exercise 3.1Programmed Exercise 3.2ProblemsUnit 4: Applications of Boolean Algebra Minterm and Maxterm ExpansionsObjectivesStudy Guide4.1 Conversion of English Sentences to Boolean Equations4.2 Combinational Logic Design Using a Truth Table4.3 Minterm and Maxterm Expansions4.4 General Minterm and Maxterm Expansions4.5 Incompletely Specified Functions4.6 Examples of Truth Table Construction4.7 Design of Binary Adders and SubtractersProblemsUnit 5: Karnaugh MapsObjectivesStudy Guide5.1 Minimum Forms of Switching Functions5.2 Two- and Three-Variable Karnaugh Maps5.3 Four-Variable Karnaugh Maps5.4 Determination of Minimum Expressions Using Essential Prime Implicants5.5 Five-Variable Karnaugh Maps5.6 Other Uses of Karnaugh Maps5.7 Other Forms of Karnaugh MapsProgrammed Exercise 5.1ProblemsUnit 6: Quine-McCluskey MethodObjectivesStudy Guide6.1 Determination of Prime Implicants6.2 The Prime Implicant Chart6.3 Petrick’s Method6.4 Simplification of Incompletely Specified Functions6.5 Simplification Using Map-Entered Variables6.6 ConclusionProgrammed Exercise 6.1ProblemsUnit 7: Multi-Level Gate Circuits NAND and NOR GatesObjectivesStudy Guide7.1 Multi-Level Gate Circuits7.2 NAND and NOR Gates7.3 Design of Two-Level NAND- and NOR-Gate Circuits7.4 Design of Multi-Level NAND- and NOR-Gate Circuits7.5 Circuit Conversion Using Alternative Gate Symbols7.6 Design of Two-Level, Multiple-Output Circuits7.7 Multiple-Output NAND- and NOR-Gate CircuitsProblemsUnit 8: Combinational Circuit Design and Simulation Using GatesObjectivesStudy Guide8.1 Review of Combinational Circuit Design8.2 Design of Circuits with Limited Gate Fan-In8.3 Gate Delays and Timing Diagrams8.4 Hazards in Combinational Logic8.5 Simulation and Testing of Logic CircuitsProblemsDesign ProblemsUnit 9: Multiplexers, Decoders, and Programmable Logic DevicesObjectivesStudy Guide9.1 Introduction9.2 Multiplexers9.3 Three-State Buffers9.4 Decoders and Encoders9.5 Read-Only Memories9.6 Programmable Logic Devices9.7 Complex Programmable Logic Devices9.8 Field-Programmable Gate ArraysProblemsUnit 10: Introduction to VHDLObjectivesStudy Guide10.1 VHDL Description of Combinational Circuits10.2 VHDL Models for Multiplexers10.3 VHDL Modules10.4 Signals and Constants10.5 Arrays10.6 VHDL Operators10.7 Packages and Libraries10.8 IEEE Standard Logic10.9 Compilation and Simulation of VHDL CodeProblemsDesign ProblemsUnit 11: Latches and Flip-FlopsObjectivesStudy Guide11.1 Introduction11.2 Set-Reset Latch11.3 Gated Latches11.4 Edge-Triggered D Flip-Flop11.5 S-R Flip-Flop11.6 J-K Flip-Flop11.7 T Flip-Flop11.8 Flip-Flops with Additional Inputs11.9 Asynchronous Sequential Circuits11.10 SummaryProblemsProgrammed Exercise 11.35Unit 12: Registers and CountersObjectivesStudy Guide12.1 Registers and Register Transfers12.2 Shift Registers12.3 Design of Binary Counters12.4 Counters for Other Sequences12.5 Counter Design Using S-R and J-K Flip-Flops12.6 Derivation of Flip-Flop Input Equations-SummaryProblemsUnit 13: Analysis of Clocked Sequential CircuitsObjectivesStudy Guide13.1 A Sequential Parity Checker13.2 Analysis by Signal Tracing and Timing Charts13.3 State Tables and Graphs13.4 General Models for Sequential CircuitsProgrammed Exercise 13.1ProblemsUnit 14: Derivation of State Graphs and TablesObjectivesStudy Guide14.1 Design of a Sequence Detector14.2 More Complex Design Problems14.3 Guidelines for Construction of State Graphs14.4 Serial Data Code Conversion14.5 Alphanumeric State Graph Notation14.6 Incompletely Specified State TablesProgrammed Exercise 14.1ProblemsUnit 15: Reduction of State Tables State AssignmentObjectivesStudy Guide15.1 Elimination of Redundant States15.2 Equivalent States15.3 Determination of State Equivalence Using an Implication Table15.4 Equivalent Sequential Circuits15.5 Reducing Incompletely Specified State Tables15.6 Derivation of Flip-Flop Input Equations15.7 Equivalent State Assignments15.8 Guidelines for State Assignment15.9 Using a One-Hot State AssignmentProblemsUnit 16: Sequential Circuit DesignObjectivesStudy Guide16.1 Summary of Design Procedure for Sequential Circuits16.2 Design Example-Code Converter16.3 Design of Iterative Circuits16.4 Design of Sequential Circuits Using ROMs and PLAs16.5 Sequential Circuit Design Using CPLDs16.6 Sequential Circuit Design Using FPGAs16.7 Simulation and Testing of Sequential Circuits16.8 Overview of Computer-Aided DesignDesign ProblemsAdditional ProblemsUnit 17: VHDL for Sequential LogicObjectivesStudy Guide17.1 Modeling Flip-Flops Using VHDL Processes17.2 Modeling Registers and Counters Using VHDL Processes17.3 Modeling Combinational Logic Using VHDL Processes17.4 Modeling a Sequential Machine17.5 Synthesis of VHDL Code17.6 More about Processes and Sequential StatementsProblemsSimulation ProblemsUnit 18: Circuits for Arithmetic OperationsObjectivesStudy Guide18.1 Serial Adder with Accumulator18.2 Design of a Binary Multiplier18.3 Design of a Binary DividerProgrammed Exercise 18.1ProblemsUnit 19: State Machine Design with SM ChartsObjectivesStudy Guide19.1 State Machine Charts19.2 Derivation of SM Charts19.3 Realization of SM ChartsProblemsUnit 20: VHDL for Digital System DesignObjectivesStudy Guide20.1 VHDL Code for a Serial Adder20.2 VHDL Code for a Binary Multiplier20.3 VHDL Code for a Binary Divider20.4 VHDL Code for a Dice Game Simulator20.5 Concluding RemarksProblemsLab Design ProblemsAppendix A: MOS and CMOS LogicAppendix B: VHDL Language SummaryAppendix C: Tips for Writing Synthesizable VHDL CodeAppendix D: Proofs of TheoremsAppendix E: Answers to Selected Study Guide Questions and ProblemsReferencesIndexDescription of the CD
